ECS-XMC/FPGA

• Add EtherCAT SubDevice functionality to your XMC equipped base board

• The EtherCAT SubDevice Controller address space is directly mapped to the PCI Express® address space.

• Easy Configuration by esd's EtherCAT MainDevice or other MainDevices

• Sample EtherCAT SubDevice Information File (ESI file in XML format) is provided

• esd's EtherCAT SubDevice API library and sample code for rapid application development are included

• The FPGA contains Bus Master DMA Support to offload the CPU from copying the output process image data into the host memory. This is utilized by the esd EtherCAT SubDevice Stack.

The ECS-XMC/FPGA is an EtherCAT SubDevice Controller board in a VITA 42.3 (XMC) form factor. It utilizes a Beckhoff IP-Core which is implemented in an Altera FPGA and configured for 8 FMMUs, 8 Sync Managers, 60 kB DPRAM and 64 bit Distributed Clocks. Other Configurations are available on request. The FPGA connects between the PCI Express bus on the XMC P15 connector and the two Ethernet interfaces on the front panel. The additional EtherCAT signals Sync and Latch are available on the secondary XMC connector P16, soldering pads or optionally on the PMC I/O connector P14.

Because of this simple hardware topology and the use of a “soft” controller the design offers a maximum of flexibility. The XMC system can act as an I/O node. An EtherCAT MainDevice can use several EtherCAT protocols like CoE, FoE and EoE to communicate with this EtherCAT SubDevice.

Via connector XMC-P16 equipped on the ECS-XMC/FPGA 20 3.3 V LVTTL I/Os are available, including the signals from the EtherCAT SubDevice Controller: 2x Sync and 2x Latch. On request the 20 XMC I/Os can be configured as 10 I/Os with 2.5 V level LVDS.

Device drivers for Windows® and Linux® with documentation and EtherCAT SubDevice examples are included in the scope of delivery. Drivers for other operating systems, especially real-time operating systems, are available on request.

EtherCAT Technology