XMC/PMC 64-bit PowerPC® T1022 Processor Board with FPGA
High-End CPU for Test and Application
NXP® PowerPC® QorIQ® T1022, 1.2 GHz, 64-bit architecture, Dual Core, Double Precision Floating Point Unit, Ethernet, ECC-RAM
Xilinx® Artix®-7 FPGA (XC7A75T) for local applications
2x Gigabit Ethernet, 1x USB 2.0 (Host)
62 I/Os at connector PMC-P4 configurable via FPGA as single ended (LVTTL) or 31 LVDS pairs
Health Features and Fallback Flash
Local voltage and temperature monitoring
Fail save firmware update by means of fallback Flash
Over temperature protection
Wide Range of Software Support
Customization on Request
- QorIQ T1014 or T1024 or T1042 are applicable
- Additional connector P6 with (e.g.) 73 LVTTL or 34 LVDS I/Os
- MRAM (512 Kbyte)
- Console RS-232 via P4
- CAN (with IRIG-B timestamp) via P4
- Up to 2x 128 MByte Flash
- Up to 2 GByte DDR3 RAM
- PMC only version, without connectors P5 and P6
- BSP for OS-9® on request
64-Bit XMC PowerPC Host CPU
The XMC-CPU/T10 is equipped with a PMC and an XMC interface. The NXP PowerPC QorIQ T1022 with 1.2 GHz features two 64-bit e5500 Power Architecture® processor cores with high-performance data path acceleration architecture (DPAA) and network peripheral interfaces. The local memory bus is 64 bits wide plus 8 bits ECC with an overall capacity of 512 Mbyte. 16 Mbyte SPI Flash for boot loader and 32 Kbit I²C EEPROM for U-Boot environment offer non-volatile memory spaces. The XMC-CPU/T10 features a second 16 Mbyte 'fallback' SPI Flash that is used for system recovery if a system crash occurs during a firmware update. Alternatively it can be used for application software.
FPGA for Local Applications
The Xilinx Artix-7 FPGA is connected to the CPU by local bus for low latency data exchange. For high bandwidth data exchange the FPGA is additionally connected via PCI Express® to the CPU. 62 LVTTL-I/Os of the FPGA are routed to the PMC-P4 connector.
The XMC interface comes with 4-lane PCIe bus and is designed according to VITA™ 42.3. The PMC interface supports 32 bit / 66 MHz PCI bus according to PCI Local Bus Specification 3.0.
The XMC-CPU/T10 is equipped with two Gigabit Ethernet interfaces accessible at the front panel, which give an excellent base for EtherCAT® applications.
The USB host port supports USB 2.0.
The Flash memory carries the standard boot program "Das U-Boot" and enables the XMC-CPU/T10 to boot various operating systems from on-board Flash, network or USB.
BSPs are available for QNX, Linux and VxWorks. The BSPs include an example source code for the FPGA. Programming of the FPGAs is done via XILINX Toolchain.
The esd EtherCAT Master Stack is available for all supported operating systems.
Customization on Request
esd offers standard PIM modules for CAN signals.
Furthermore a CAN IP-core (CAN esdACC) is available on request, implemented in a customized configuration (number of CAN nodes, routing FPGA ↔ P4).
I/Os via P6
Additional 73 LVTTL I/Os at connector P6 or 34 LVDS I/Os are available on request as well as a Serial ATA interface.
Furthermore other CPU-types (T1014, T1042) are applicable, also an additional MRAM and other serial interfaces (RS-232) via P4.
Up to 2x 128 MByte Flash is available on request.
Up to 2 GByte DDR3 RAM is available.
The XMC-CPU/T10 can be produced without the connectors P5 and P6 if the space on the carrier is limited.
All these options are available for customized series production in reasonable quantities.
Please contact our sales team for detailed information.