- XILINX® Zynq® Ultrascale+TM CG MPSoC, 1.3 GHz, Dual Core A53 Application Processor Unit (APU) + Dual-Core Realtime Processor Unit (RPU)
- Powerful Xilinx FPGA for flexible hardware design, integrated in CPU
- 4x GB Ethernet, 1x serial interface
- Over 120 I/Os at the P4 and P6 transfer connectors, configurable via FPGA as single-ended (LVTTL) or 50 LVDS pairs
- Linux® and VxWorks® BSPs available
- Sample source code for FPGA included in Linux BSP
- EtherCAT® Master available
- Universal boot loader: "Das U-Boot"
- PMC instead of XMC
- CAN IP core accessible via P4 or P6
- IRIG-B IP core accessible via P4 or P6
- Other CPU types of the Zynq UltraScale+ MPSoC family
- Extended temperature range
The XMC form factor CPU/Zulu features an XILINX Zynq Ultrascale+ CG multiprocessor (system-on-chip) with 1.3 GHz clock frequency.
The 32-bit wide DDR4 RAM offers a total capacity of 1 GByte.
In addition, the XMC CPU/Zulu offers 64 MByte SPI flash for boot loaders and 32 KBit I²C EEPROM for submarine environments.
The 16 GByte eMMC mass storage of the XMC-CPU/Zulu is used for operating system, file system and application software.
Two Gigabit Ethernet interfaces are accessible via the front panel of the XMC CPU/Zulu and provide an excellent basis for EtherCAT® applications.
Two additional Ethernet interfaces (Rear-IO) are accessible via the XMC connector P6. These two Rear-IO Ethernet interfaces are not galvanically isolated.
Two of the GB Ethernet interfaces (1x front and 1x rear IO each) are routed through the FPGA. This allows special Ethernet IP cores to be implemented.
The serial interface with USB mini connector is designed as a terminal interface. The USB mini type-B connector is easily accessible in the front panel of the XMC CPU/Zulu.
The flash memory contains the standard boot program "The U-Boot" and thus enables the XMC CPU/Zulu to boot various operating systems via on-board flash, network or eMMC.
BSPs are available for Linux® and VxWorks®. The BSPs contain sample source code for the FPGA. The FPGA is programmed via XILINX toolchain.
The esd EtherCAT master stack is available for many operating systems.
We offer customized options for reasonable quantities. Please contact our sales team for detailed information.
esd electronics offers standard PIM modules for CAN signals. Furthermore, a CAN IP core (CAN esdACC), which is configurable in wide ranges (number of CAN nodes, routing FPGA ↔ P4), is available for the FPGA of the XMC CPU/Zulu on request.
An IRIG-B IP core from esd electronics can be implemented in the FPGA. The physical interface of IRIG-B must be provided externally via a PIM module. An esd PIM module is available on request.
- Other CPU types
Further CPU types (ZU2EG, ZU3CG and ZU3EG) can be used.
- Erweiterter Temperaturbereich
Durch Einsatz dafür geeigneter Bauteile kann der Temperaturbereich auf -40 °C bis 75 °C erweitert werden.
Instead of the XMC interface, a PMC interface (according to IEEE Std 1386-2001) is set up via the P1 and P2 connectors. The PCI bus conforms to the PCI Local Bus Specification 3.0 and is designed for 3.3 V (5 V tolerant) at 32-bit wide bus and 33/66 MHz. It also has PCI bus master capability.
The PMC interface supports 32 bit / 66 MHz PCI bus according to PCI Local Bus Specification 3.0.
The Rear IO Ethernet signals are connected via P6. For standard Ethernet cabling a PIM module from esd is available on request. The PIM module is equipped with RJ45 jack and integrated Ethernet transformers.
In addition, an RTC can be equipped. A backup battery can be connected via connectors P4 and P6.
Please contact our sales team for board support packages for other real-time operating systems (e.g. QNX).