XMC Ultrascale+ Zynq® MPSoC Board with integrated FPGA
High-End CPU for Test and Application
XILINX® Zynq® Ultrascale+TM CG MPSoC, 1.3 GHz, Dual Core A53 Application Processor Unit (APU) + Dual Core Realtime Processor Unit (RPU)
Powerful Xilinx FPGA for flexible hardware design, integrated in CPU
4x GB-Ethernet, 1x serial interface
More than 120 I/Os at connectors P4 and P6 configurable via FPGA as single ended (LVTTL) or 50 LVDS pairs
Local voltage and temperature monitoring
Over temperature protection
Customization on Request
• PMC instead of XMC
• CAN IP-Core via P4 or P6
• IRIG-B IP-Core via P4 or P6
• Other CPU-types of the Zynq UltraScale+ MPSoC family
• Extended temperature range
64-Bit XMC ARM® Host CPU
The XMC-CPU/Zulu in XMC form factor comes with a XILINX Zynq Ultrascale+ CG multiprocessor system-on-chip with 1.3 GHz core frequency.
The local memory bus is 32 bits wide with an overall capacity of 1 Gbyte.
64 Mbyte SPI Flash for boot loader and 32 Kbit I²C EEPROM for U-Boot environment.
XMC-CPU/Zulu features a 16 Gbyte eMMC memory which is used for operating system, file system and application software.
The XMC interface comes with quad-lane PCIe bus and is designed according to VITATM 42.3.
Two Gigabit Ethernet interfaces are accessible via the front panel of the XMC-CPU/Zulu. This gives an excellent base for EtherCAT® applications.
Two additional rear IO Ethernet interfaces are accessible via the XMC connector P6. The rear IO Ethernet interfaces come without electrical isolation.
Two of the GB Ethernet interfaces (one front, one rear) are rooted through the FPGA. Therefore special Ethernet IP-cores can be implemented.
A serial interface, designed as terminal interface, is accessible via a USB Mini connector. This USB Mini type-B connector is easily accessible via the front panel of the XMC-CPU/Zulu.
The Flash memory carries the standard boot program “Das U-Boot” and enables the XMC-CPU/Zulu to boot various operating systems from on-board Flash, network or eMMC.
BSPs are available for Linux and VxWorks. The BSPs include an example source code for the FPGA. Programming of the FPGAs is done via XILINX Toolchain.
The esd EtherCAT Master Stack is available for various operating systems.
Customization on Request
Customized options are available for customized series production in reasonable quantities. Please contact our sales team for detailed information.
esd offers standard PIM modules for CAN signals. Furthermore a CAN IP-core (CAN esdACC), which is configurable (number of CAN nodes, routing FPGA ↔ P4), is available for the on-board FPGA on request.
An IRIG-B IP Core by esd electronics can be implemented in the FPGA. The physical interface of IRIG-B has to be provided externally via a PIM module. An esd PIM module is available on request.
- Further CPU Types
Furthermore other CPU-types (ZU2EG, ZU3CG and ZU3EG) are applicable.
- Extended Temperature Range
The temperature range can be extended from -40 °C up to 75 °C.
PMC according to IEEE Std 1386-2001 instead of XMC interface via connectors P1 and P2. The PCI bus conforms to PCI Local Bus Specification 3.0, 32 bit 33/66
MHz, 3.3 V (5 V tolerant), PCI bus master capability. The PMC interface supports 32 bit / 66 MHz PCI bus according to PCI Local Bus Specification 3.0.
The rear IO Ethernet signals are connected via P6. To connect standard Ethernet cabling an esd PIM module is available on request. The PIM module comes with an RJ45 connector and the Ethernet transformers on-board.
An additional RTC can be equipped. A backup battery can be connected via P4 and P6.
Please contact our Sales-Team for board support packages of other real-time operating systems (e.g. QNX®).